The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner. The various layers define circuit components or devices such as transistors.
After the individual devices have been fabricated on the substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally known as “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques. In one interconnection process, called a “dual damascene” technique, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point.
While there exist many variations of a dual-damascene process flow, the process typically begins with deposition of a silicon dioxide dielectric layer of desired thickness which corresponds to the thickness for the via or vias to be etched in the dielectric layer. Next, a thin etch stop layer, typically silicon nitride, is deposited on the dielectric layer. Photolithography is then used to pattern via openings over the etch stop layer, after which dry etching is used to etch via openings in the etch stop layer.
The patterned photoresist is then stripped from the etch stop layer after completion of the etch. A remaining dielectric layer the thickness of which corresponds to the thickness of the trench for the metal interconnect lines is then deposited on the etch stop layer, and photolithography followed by dry etching is used to pattern the trenches in the remaining dielectric layer and the vias beneath the trenches. The trench etching stops at the etch stop layer, while the vias are etched in the first dielectric layer through the openings in the etch stop layer and beneath the trenches.
Next, a barrier material, typically Ta, TaN, W, WN, Ti, TiN, TiZr or TiZrN is deposited on the sidewalls and bottoms of the trenches and vias using ionized PVD. A uniform copper seed layer is then deposited on the barrier layer using CVD. After the trenches and vias are filled with copper in a single copper inlay step, the copper overburden extending from the trenches is removed and the upper surfaces of the metal lines planarized using CMP.
In the dual damascene process described above, the vias and the trenches are etched in the same step, and the etch stop layer defines the bottom of the trenches. In other variations, the trench is patterned and etched after the via. In the single damascene process, the vias and trenches are individually, rather than simultaneously, filled with copper inlays.
A significant advantage of the dual-damascene process is the creation of a two-leveled metal inlay which includes both via holes and metal line trenches that undergo copper fill at the same time. This eliminates the requirement of forming the trenches for the metal interconnect lines and the holes for the vias in separate processing steps. The process further eliminates the interface between the vias and the metal lines.
Another important advantage of the dual-damascene process is that completion of the process typically requires 20% to 30% fewer steps than the traditional aluminum metal interconnect process. Furthermore, the dual damascene process omits some of the more difficult steps of traditional aluminum metallization, including aluminum etch and many of the tungsten and dielectric CMP steps. Reducing the number of process steps required for semiconductor fabrication significantly improves the yield of the fabrication process, since fewer process steps translate into fewer sources of error that reduce yield.
In both the single damascene and dual damascene techniques, the via sidewalls and via bottom are typically subjected to a reactive clean and physical argon ion bombardment process prior to deposition of the barrier layer onto those surfaces. This is illustrated in FIG. 1A, in which a dual damascene structure 10 is subjected to argon ion bombardment prior to deposition of a metal barrier layer 2 (FIG. 1B) on the structure 10. The dual damascene structure 10 includes a typically copper conductive layer 20, on which is sequentially deposited a via dielectric layer 22 and a trench dielectric layer 24. A via opening 26 and a trench opening 28 are etched in the via dielectric layer 22 and the trench dielectric layer 24, respectively.
During the argon ion bombardment cleaning process, argon ions 18 are directed against the trench sidewalls 12, the via sidewalls 14 and the via bottom 16 of the structure 10. However, the argon ion bombardment process has a tendency to cause re-sputtering of metal particles 21 from the conductive layer 20 at the via bottom 16, onto the via sidewalls 14. This disrupts the structural integrity of the damascene profile, adversely affecting device reliability and performance.
As a result of the metal re-sputtering of the conductive layer 20 which frequently occurs during the argon ion bombardment cleaning process, the barrier layer 2 subsequently deposited on the sidewalls and bottom of the trench opening 28 and via opening 26 frequently forms overhangs (excessive flat field thickness) 4 at the upper corners of the trench opening 28 and via opening 26; non-uniform sidewall coverage; and an excessively thick bottom layer 3 at the bottom of the via opening 26.
One solution to this problem involves re-sputtering of the metal atoms in the barrier layer 2 using argon to improve sidewall coverage and reduce the thickness of the barrier layer at the bottom of the via opening. However, this re-sputtering process has a tendency to further damage the damascene structure profile, thereby increasing the sheet resistance of copper interconnects subsequently formed in the via opening and trench opening. This phenomenon is particularly problematic in the fabrication of metal interconnects having ever-shrinking sizes, as is the case with regard to interconnects having a line width on the nanometer scale (such as 90 nm and 60 nm technology).
Accordingly, particularly in the fabrication of damascene or other contact structures for nanometer-scale interconnect technology, a novel process for re-distributing a barrier layer is needed to eliminate or reduce overhang in the barrier layer at the upper corners of via and trench openings; enhance uniformity in sidewall coverage; and reduce the thickness of the barrier layer at the bottom of the via openings.
An object of the present invention is to provide a novel process which is suitable for re-distributing a metal barrier layer deposited on the sidewalls and bottoms of trenches and vias or other contact openings in a contact structure.
Another object of the present invention is to provide a novel process which is suitable for re-distributing a metal barrier layer to fabricate metal interconnects of low electrical resistance on a substrate.
Still another object of the present invention is to provide a novel barrier layer re-distribution process which is effective in enhancing sidewall coverage and eliminating or reducing overhangs and bottom thickness in a barrier layer deposited on the sidewalls and bottom of trenches and vias in a damascene or other contact structure.
Yet another object of the present invention is to provide a novel barrier metal re-distribution process which may include depositing a barrier metal on the sidewalls and bottoms of a trench opening and via opening or other contact opening, subjecting the barrier layer to a first re-sputter step using both argon and barrier metal ion bombardment, and subjecting the barrier layer to a second re-sputter step using argon ion bombardment only.
Another object of the present invention is to provide a novel barrier metal re-distribution process which includes depositing a barrier metal on the sidewalls and bottoms of a trench opening and via opening or other contact opening on a substrate; placing the substrate in a PVD (physical vapor deposition) chamber; subjecting the barrier layer to a first re-sputter step using both argon and tantalum ion bombardment, with the DC source of the PVD chamber on; and subjecting the barrier layer to a second re-sputter step using argon ion bombardment only, with the DC source of the PVD chamber off.